Challenges and Opportunities in HPC Memory Systems:
Innovation, Moore's Law, and a Vision for Exascale Data Movement
Seminar by Dr. Richard Murphy, Micron
Tuesday, May 3, 2016 from 12:00pm-2:00pm
Steinman Hall Lecture Room, Andy Grove School of Engineering
160 Convent, New York, NY 10031
Memory and storage systems hold the key to addressing performance in the vast majority of real-world applications. Since the beginning of computing, the von Neumann Bottleneck has marked a strong bifurcation of computing and memory technology. In the early days, this was acceptable, as both technologies had a long path to maturity. However, things have changed and memory and storage are now the most critical components in the system, not processors. Over the last five decades, Moore's Law and Dennard Scaling, have driven the computing and semiconductor business. The end of Dennard Scaling in 2003 began the transition to modern multicore architectures, and as providing more transistors per die becomes economically harder the trend toward architectural innovation will continue. Technologically, better architecture is the only way to continue to provide sustained growth in computing performance. Concurrent with the change to the underlying technology, the way we use computers has also changed. We have moved from a regime requiring increases in the performance of calculations, into one which requires better handling of data. While Moore's law provided a doubling of transistors every 18 to 24 months (which historically resulted in a doubling of "computer performance" in about the same timeframe), today data doubles every nine months or less. This More-than-Moore's growth rate further emphasizes the importance of architecture in addressing the problem, leading to the potential for innovation. This talk will discuss a few of those challenges, a set of key architectural concepts that can be applied at the system level to address them, and how emerging memory technologies (e.g. 3D XPoint) might impact computing..
Dr. Richard Murphy is Director of Advanced Computing Solutions Pathfinding at Micron Technology, Inc.. His group focuses on identifying advanced technologies to bring to market in the 3-5 year timeframe, particularly Processing-In-Memory (PIM) capabilities. The group takes an application-centric approach by quantifying the end-user benefit to adopting advanced technologies, with a particular focus on data analytics, cybersecurity, and mobile.
Previously, Murphy was a Principal Member of Technical Staff at Sandia National Laboratories, a technical staff member at SUN Microsystems and QUALCOMM. While at Sandia, he served as the Principal Investigator the lab's DARPA UHPC Program (X-caliber), the lab's Extreme-scale Computing Grand Challenge (XGC), and other national-scale projects for DOD and DOE.
Murphy's interests include advanced R&D of computer architecture, memory systems, supercomputers, data analytics platforms at all scales, and disruptive mobile technologies. He has led several large multidisciplinary/cross-functional teams to successfully deploy new technologies. In 2010, he cofounded the Graph 500 benchmark which has helped to push the industry to identify and solve performance challenges with large-scale graph problems.
Murphy is Adjunct Faculty in ECE at the Georgia Tech and New Mexico State University, and in CS at Boise State University. He has authored over two dozen papers and numerous patents. He received a PhD in computer science and engineering, a MS, BS, and BA from the University of Notre Dame and is a Senior Member of the IEEE.
*This seminar is free of charge for all CUNY Faculty, Staff and Students.
This event is brought to you by the CUNY HPCC, City College of New York, College of Staten Island and the CUNY Research Foundation.